Sponsor: SRC
PIs: C.J. Richard Shi
Period: Sept.2013 to Sept 2016

Objectives: Mixed-Signal design verification and post-silicon debugging processes rely heavily on the use of various circuit simulators. The total simulation and debugging time depend on both CPU time per simulation run and the simulation test vector (stimulus) length. Existing work has primarily focused on fast simulation algorithms and simulation with multiple CPU cores to reduce CPU time per simulation. The objective of this project is the development of systematic methods of deriving the minimal length simulation tests for mixed-signal functional verification and post-silicon debugging.

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