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Design and Optimize CMOS RF Receiver Front-end of WCDMA in TSMC 90nm.

A complete fully differential RF receiver front-end, including a low-noise amplifier, voltage- controlled oscillator, and passive mixer, designed in TSMC 90nm CMOS technology. The design specification of this RF receiver chain is in accordance with the requirement of WCDMA standard. A fully differential low-noise amplifier with inductive degeneration and capacitor compensation is implemented. For the LNA, the post-layout simulation shows that the power consumption is around 11.8mW with 1.25V compensation is implemented. For the LNA, the post-layout simulation designates that the power consumption is around 11.8mW with 1.25V power supply. The maximum noise figure is 2.09dB, and reflection coefficient (S11) is -15.3dB. The voltage gain at 2.1GHz (S21) is over 20dB. The input third-order intercept point (IIP3) is 10dBm at with two tonnes (2.101GHz and 2.102GHz) input. Static current of the LC tank based voltage- controlled oscillator (VCO) is 1.266mA with 1.2V power supply. The phase noise of the VCO is -156.516 at 130MHz. The figure of merit (F OM ) of the VCO is -337.052. For passive mixer, the conversion gain is 20.49dB. The input third-order intercept point (IIP3) of the mixer is 6.69 dBm with two input tones of 2.15GHz and 2.154GHz. The figure of merit (F OM ) of the mixer is 222.173. The noise figure of the RF receiver chain is 5.66dB. The input third-order intercept point (IIP3) for the RX chain is -11.1dB. Simulations and measurement result demonstrates that the circuit fully meets the design specifications.

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